The present invention relates to a gradation display reference voltage generating circuit and a liquid crystal driving device, and in particular to a gradation display reference voltage generating circuit used for a liquid crystal display device employing a line inversion method, and a liquid crystal driving device using it.
Conventionally, there is a gradation display reference voltage generating circuit using intermediate voltages obtained by resistance division for driving the liquid crystal in an active matrix liquid crystal display device (see, for example, JP 11-272243 A).
In the gradation display reference voltage generating circuit, the resistors used for resistance division have a resistance ratio called gamma (γ) correction, and the optical characteristic of the liquid crystal material is corrected according to the resistance ratio in order to achieve more natural gradation display.
The configuration of a liquid crystal display device comprising the gradation display reference voltage generating circuit, the configuration of a thin film transistor (TFT) liquid crystal panel in the liquid crystal display device, liquid crystal driving waveforms for the liquid crystal panel, and the configuration of source drivers for the liquid crystal panel will be described below.
FIG. 6 is a block diagram showing the configuration of a TFT liquid crystal display device which is a typical example of a conventional active matrix liquid crystal display device. The liquid crystal display device consists of a liquid crystal display section and a liquid crystal driving circuit (liquid crystal driving section) for driving it. The liquid crystal display section has a TFT liquid crystal panel 101. In the liquid crystal panel 101, liquid crystal display elements (not shown) and a counter electrode (common electrode) 102 described later in detail are provided.
On the other hand, the liquid crystal driving circuit includes a source driver section 103 and a gate driver section 104 constituted by integrated circuits (ICs), a controller 105, and a liquid crystal driving power supply 106. The controller 105 enters display data D and a control signal S1 into the source driver section 103, while entering a control signal S2 into the gate driver section 104. The controller 105 also enters a horizontal synchronizing signal (not shown) into the source driver section 103 and the gate driver section 104.
In the liquid crystal display device configured as described above, display data entered into the device from the outside is supplied to the source driver section 103 as digital signal display data D through the controller 105. The source driver section 103 timeshares the input display data D so as for the display data to be latched in the 1st source driver SD11 to the nth source driver SD1n, and then carries out digital-analog (D/A) conversion of the display data in synchronization with the horizontal synchronizing signal. Analog voltages for gradation display (referred to as “gradation display voltages” hereinafter) obtained by D/A conversion of the timeshared display data D are output to corresponding liquid crystal display elements in the liquid crystal panel 101 through source signal lines (not shown).
FIG. 7 shows the configuration of the liquid crystal panel 101 shown in FIG. 6. The liquid crystal panel 101 is provided with pixel electrodes 111, pixel capacitors 112, TFTs 113 for on/off control of application of voltages to the pixel electrodes 111, source signal lines 114, gate signal lines 115, and a counter electrode 116 (corresponding to the counter electrode 102 shown in FIG. 6). In this configuration, a liquid crystal display element A for one pixel consists of a pixel electrode 111, a pixel capacitor 112 and a TFT 113.
Gradation display voltages described above corresponding to the brightness levels of pixels as displaying objects are supplied from the source driver section 103 in FIG. 6 to the source signal lines 114. On the other hand, scanning signals for successively turning on TFTs 113 arranged in the column direction are supplied from the gate driver section 104 to the gate signal lines 115. Then, through the TFTs 113 in the ON state, the gradation display voltages of the source signal lines 114 are applied to the pixel electrodes 111 connected with the drains of the TFTs 113, so that the pixel capacitors 112 between the pixel electrodes 111 and the counter electrode 116 are charged. Thus, the light transmittance of the liquid crystal is changed according to the gradation display voltages, providing pixel display.
FIGS. 8 and 9 each show an example of a liquid crystal driving waveform (The figures show cases that the voltage of the counter electrode is constant in order to illustrate that electric charge is stored into a pixel capacitor for display. The display principles in these cases are similar to that in a line inversion method of inverting the polarity of the counter electrode described later although the waveforms are different from those in the line inversion method). In FIGS. 8 and 9, the reference numerals 121, 125 each denote a driving waveform of the source driver section 103 (shown in FIG. 6), while the reference numerals 122, 126 each denote a driving waveform of the gate driver section 104. Furthermore, the reference numerals 123, 127 each denote an electric potential of the counter electrode 116, and the reference numerals 124, 128 each denote a voltage waveform of a pixel electrode 111. A voltage applied to the liquid crystal material is an electric potential difference between a pixel electrode 111 and the counter electrode 116, and is indicated by hatched lines in the figure.
For example, in the case of FIG. 8, a TFT 113 (shown in FIG. 7) is turned on only for a period of time during which the driving waveform 122 of the gate driver section 104 (shown in FIG. 6) is at the “high level”, so that a voltage which is the difference between the potential of the driving waveform 121 of the source driver section 103 and the potential 123 of the counter electrode 116 is applied to the pixel electrode 111. Consequently, the driving waveform 122 of the gate driver section 104 becomes the “low level”, so that the TFT 113 is turned off. In this case, the above voltage is maintained because of the existence of the pixel capacitor 112 in the pixel.
The same thing can be said for the case of FIG. 9. However, the voltage applied to the liquid crystal material in the case of FIG. 8 is different from that in the case of FIG. 9, and the applied voltage in the case of FIG. 8 is higher than that in the case of FIG. 9. As is apparent from above, the voltage applied to the liquid crystal material is varied as an analog voltage, so that the light transmittance of the liquid crystal is varied in an analog fashion, realizing multi-gradation display. In this connection, the number of possible gradations for display is dependent on the number of analog voltages to be selectively applied to the liquid crystal material.
FIG. 10 is a block diagram of one of the 1st to nth source drivers SD11 to SD1n shown in FIG. 6. Input digital signal display data D includes R (red), G (green), and B (blue) display data (DR, DG, and DB). The display data D is once latched by the input latch circuit 131 and is then stored in the sampling memory 133 by time sharing in synchronization with the operation of the shift register 132 shifted by the control signal S1 (start pulse SP and clock CK) from the controller 105 (shown in FIG. 6). The stored display data is then transferred to the hold memory 134 by one operation based on the horizontal synchronizing signal (not shown) from the controller 105. The notation S denotes a cascade output.
The gradation display reference voltage generating circuit 139 shown in FIG. 10 generates reference voltages of various levels based on a voltage VR supplied from an external reference voltage generating circuit (corresponding to the liquid crystal driving power supply 106 in FIG. 6). Data in the hold memory 134 is sent out to the digital-analog (D/A) conversion circuit 136 through the level shifter circuit 135 and is then converted to analog voltages based on the reference voltages of various levels received from the gradation display reference voltage generating circuit 139. The analog voltages are output as the gradation display voltages, by the output circuit 137, from the liquid crystal driving voltage output terminal 138 to the source signal lines 114 of the liquid crystal display elements A (shown in FIG. 7). That is, the number of levels of the reference voltages results in the aforementioned number of possible gradations for display.
FIG. 11 shows the configuration of the gradation display reference voltage generating circuit 139 for generating a plurality of reference voltages as described above to produce intermediate voltages. The gradation display reference voltage generating circuit 139 in FIG. 11 is designed to generate 64 levels of reference voltages.
The gradation display reference voltage generating circuit 139 consists of 9 halftone voltage input terminals indicated by V0, V8, V16, V24, V32, V40, V48, V56 and V63, resistance elements R0 to R7 having a resistance ratio for γ correction, and 64 resistors (not shown) connected eight by eight in series between both terminals of each of the resistance elements R0 to R7. As described above, a resistance ratio called γ correction is stored in the source driver section 103, providing the liquid crystal driving output voltage for conversion of display data to the gradation display voltages with a polygonal line characteristic. Thus, the optical characteristic of the liquid crystal material is corrected with the resistance ratio, so that natural gradation display which matches the optical characteristic of the liquid crystal material can be achieved. An example of the characteristic of the liquid crystal driving output voltage of the conventional gradation display reference voltage generating circuit 139 is shown in FIG. 12. In FIG. 12, the horizontal axis indicates the gradation display data (digital input), and the vertical axis indicates the liquid crystal driving output voltage (analog voltage).
By the way, in the case of display by liquid crystal, the liquid crystal must be driven in an alternating fashion, that is, by voltages the polarities of which vary alternately such that burn-in is prevented. Methods of driving TFT liquid crystal in an alternating fashion mainly include a line inversion method and a dot inversion method.
In the line inversion method, a liquid display line is driven by voltages having the same polarity, and the next line is driven by voltages having a polarity opposite to those of the preceding line. In the dot inversion method, the polarities of driving voltages vary between adjacent pixels of the liquid crystal. In the line inversion method, the polarity of the counter electrode (an electrode common to the liquid crystal pixels) is inverted every drive line, so that the driving voltage of the liquid crystal driver can be of the order of 5 V.
On the other hand, in the dot inversion method, it is necessary to change the polarity every output of the source driver, so that the driving voltage is required to be of the order of plus 5 V to minus 5 V (10 V in total).
In the dot inversion method, the current consumption becomes large by the high voltage as described above, and therefore various methods of reducing the current have been proposed. For example, in JP 8-263013 A, a method is described in which taking advantage of the fact that the output polarity of each of the lines of the source driver is inverted and is different from those of adjacent output terminals, when the output polarities are changed, short circuits are established between output terminals to neutralize the electric charges of the loads connected with the output terminals in order to reduce the electric currents passing through the loads when voltages having inverse polarities are applied to the loads. Furthermore, in JP 8-272339 A, a method is described in which the outputs are once made to be at the ground level at polarity inversion to reduce the current consumption.
In contrast to this, in the line inversion method, there is an advantage that the current consumption becomes lower by the low voltage and there is no difference in polarity between adjacent output terminals unlike the dot inversion method, so that it is not necessary to establish short circuits between adjacent output terminals at polarity inversion or to bring the output terminals to the GND level during polarity inversion as in the dot inversion method.
When liquid crystal is driven by the line inversion method, it is necessary to invert the polarity of a liquid crystal driving voltage for each of the lines. Polarity inversion is made in such a manner that voltages for various gradations are made by resistance division of a liquid crystal driving voltage, and the voltage between both ends of the resistors for the resistance division is changed, or the gradation selection signal data is inverted. For polarity inversion by such a method, it is required that gamma (γ) characteristics before and after the polarity inversion are almost equal.
In a gradation display reference voltage generating circuit having only one circuit for producing gradation display voltages, however, if the γ characteristic of the panel in the positive polarity is different from that in the negative polarity, the output voltages for the gradation display voltages should be corrected every polarity inversion, or should be adjusted to be at levels causing no display problem in both of the positive and negative polarities. For this reason, it is necessary to provide, as shown in FIG. 11, a plurality of intermediate voltage input terminals (V0, V8, V16, V24, V32, V40, V48, V56, and V63) to input correction voltages from the outside in order to correct the output voltages to voltages which match the γ characteristics.